hardware timed sampling and time-stamping of GPIO 0-31 every 5
us
hardware timed PWM on all of GPIO 0-31
hardware timed servo pulses on all of GPIO 0-31
callbacks on GPIO 0-31 level change (time accurate to a few us)
notifications via pipe on GPIO 0-31 level change
callbacks at timed intervals
reading/writing all of the GPIO in a bank (0-31, 32-53) as a single operation
GPIO reading, writing, modes, and internal pulls
socket and pipe interfaces for the bulk of the functionality
waveforms to generate GPIO level changes (time accurate to a few us)
software serial links using any user GPIO
rudimentary permission control through the socket and pipe
interfaces
piscope is a logic analyser (digital
waveform viewer).
ALL GPIO are identified
by their Broadcom
number. See
elinux.org
Bank 1 contains GPIO 0-31. Bank 2 contains GPIO
32-53.
|
GPIO | pin | pin | GPIO | |
3V3 | - | 1 | 2 | - | 5V |
SDA | 0 |
3 | 4 | - | 5V |
SCL | 1 |
5 | 6 | - | Ground |
4 | 7 | 8 | 14 | TXD | |
Ground | - | 9 | 10 | 15 | RXD |
ce1 | 17 | 11 | 12 | 18 | ce0 |
21 | 13 | 14 | - | Ground | |
22 | 15 | 16 | 23 | ||
3V3 | - |
17 | 18 | 24 | |
MOSI | 10 | 19 | 20 | - | Ground |
MISO | 9 | 21 | 22 | 25 | |
SCLK | 11 | 23 | 24 | 8 | CE0 |
Ground | - | 25 | 26 | 7 | CE1 |
|
GPIO | pin | pin | GPIO | |
3V3 | - | 1 | 2 | - | 5V |
SDA | 2 | 3 | 4 | - | 5V |
SCL | 3 | 5 | 6 | - | Ground |
4 | 7 | 8 | 14 | TXD | |
Ground | - | 9 | 10 | 15 | RXD |
ce1 | 17 | 11 | 12 | 18 | ce0 |
27 | 13 | 14 | - | Ground | |
22 | 15 | 16 | 23 | ||
3V3 | - |
17 | 18 | 24 | |
MOSI | 10 | 19 | 20 | - | Ground |
MISO | 9 | 21 | 22 | 25 | |
SCLK | 11 | 23 | 24 | 8 | CE0 |
Ground | - | 25 | 26 | 7 | CE1 |
|
GPIO | pin | pin | GPIO | |
5V |
- | 1 | 2 | - | 3V3 |
SDA |
28 | 3 | 4 | 29 | SCL |
30 | 5 | 6 | 31 | ||
Ground |
- |
7 | 8 | - |
Ground |
|
GPIO | pin | pin | GPIO | |
3V3 | - | 1 | 2 | - | 5V |
SDA | 2 | 3 | 4 | - | 5V |
SCL | 3 | 5 | 6 | - | Ground |
4 | 7 | 8 | 14 | TXD | |
Ground | - | 9 | 10 | 15 | RXD |
ce1 | 17 | 11 | 12 | 18 | ce0 |
27 | 13 | 14 | - | Ground | |
22 | 15 | 16 | 23 | ||
3V3 | - |
17 | 18 | 24 | |
MOSI | 10 | 19 | 20 | - | Ground |
MISO | 9 | 21 | 22 | 25 | |
SCLK | 11 | 23 | 24 | 8 | CE0 |
Ground | - | 25 | 26 | 7 | CE1 |
ID_SD | 0 | 27 | 28 | 1 | ID_SC |
5 | 29 | 30 | - | Ground | |
6 | 31 | 32 | 12 | ||
13 | 33 | 34 | - | Ground | |
miso | 19 | 35 | 36 | 16 | ce2 |
26 | 37 | 38 | 20 | mosi | |
Ground | - | 39 | 40 | 21 | sclk |
All 54 GPIO may be physically accessed. Some are reserved
for system use - refer to the Compute Module documentation.
Only GPIO 0-31 are supported for hardware timed sampling, PWM,
servo pulses, alert callbacks, waves, and software serial
links.
There are several third party projects which provide wrappers
for pigpio.
Some are listed here:
The PWM and servo pulses are timed using the DMA and PWM/PCM peripherals. This use was inspired by Richard Hirst's servoblaster kernel module.